The present invention relates to semiconductor processing, and more particularly, to forming a globally planar surface over low density field areas on the wafer.
Chemical-mechanical planarization (xe2x80x9cCMPxe2x80x9d) processes remove material from the surface of a wafer in the production of integrated circuits. In a typical CMP process a wafer is exposed to an abrasive medium under controlled chemical, pressure, velocity and temperature conditions. One abrasive medium used in CMP processes is a slurry solution with small, abrasive particles that abrade the surface of the wafer, and chemicals that etch and/or oxidize the surface of the wafer. Another abrasive medium used in CMP processes is a generally planar planarizing substrate made from a relatively porous matrix material, such as blown polyurethane. To increase the abrasiveness of planarizing substrates, abrasive particles are embedded into the matrix material. Thus, when the wafer moves with respect to the abrasive medium, material is removed from the surface of the wafer mechanically by the abrasive particles in the substrate and/or the slurry, and chemically by the chemicals in the slurry.
In some new CMP processes, a planarizing liquid without abrasive particles is used with an abrasive substrate covered with fixed abrasive particles. The present invention is applicable to any CMP process that removes material from the surface of the wafer.
One problem with CMP processing is that the surface of the wafer may not be uniformly planar over field areas that have a low density of device features. The surface over low density field areas is typically not as planar as that over array areas with a high density of device features because the greater distance between high points on the wafer in low density fields allows the polishing substrate to dish between the features.
FIG. 1 illustrates a specific application of a CMP process over a low density field on a wafer 20 that has a substrate 22 and a number of features 24 positioned apart from one another by a distance xe2x80x9cdxe2x80x9d. The top of the substrate 22 and the top of the device features 24 define a front face 26 of the wafer 20. In the low density field on the wafer 20, the distance d between the features 24 is relatively large such that the front face 26 has a low region 27 between the device features 24 and high points 28 defined by the tops of the device features 24. The substrate 22 and the device features 24 are covered by a fill layer 30 that conforms to the contour of the front face 26 to form a depression 34 over the low region 27 and a top surface 36 over the high points 28 of the front face 26.
When the wafer 20 is planarized with a CMP process, a planarizing substrate 40 removes material from the fill layer 30 to form a finished surface over the substrate 22 and the device features 24. The polishing substrate 40, however, partially conforms to the profile of the fill layer 30 such that a planarizing surface 42 of the planarizing substrate 40 penetrates into the depression 34 of the fill layer 30. As the CMP process continues, the profile of the depression 34 is at least partially maintained throughout the fill layer 30 until a finished surface 32(a) is formed over the substrate 22 and the device features 24. The finish surface 32(a) accordingly xe2x80x9cdishesxe2x80x9d between the device features 24 such that the elevation of the surface 32(a) over the low region 27 is lower than over the device features 24.
The extent of xe2x80x9cdishingxe2x80x9d is a function of the compressibility of the polishing substrate 40 and the distance between the device features 24. In general, more compressible polishing substrates and larger distances between device features produce greater dishing on the surface of the wafer. Therefore, it is difficult to form a planar surface over low density fields.
One existing technique for reducing dishing over low density fields is to form raised support structures over the low regions in the low density fields. In addition to the structure shown in FIG. 1, a raised support feature is fabricated over the low region in the low density field by:
(1) depositing a cover layer over the fill layer;
(2) depositing a top layer over the cover layer;
(3) photo-patterning resist on the top layer aligned with the low region of the low density field;
(4) selectively etching the top layer to expose the cover layer over the high points on the wafer;
(5) removing the remaining resist from the wafer to form a mask segment from the remaining portion of the top layer over the low region;
(6) performing a first CMP of the cover layer which endpoints at the mask segment of the top layer over the low density field;
(7) etching exposed areas of the fill layer and the mask segment from the wafer to form a raised feature over the low region; and
(8) performing a second CMP of the raised feature to a final endpoint.
One problem with forming raised support features using this technique is that lithographic processing is expensive. Lithographic processing machines are typically very expensive, and lithographic processes are time-consuming because the resist material must be deposited, patterned, and then washed to form a mask in the desired pattern.
Another problem with this technique is that the lithographic pattern may not be appropriately aligned with the low regions on the surface of the wafer. The resulting raised support features may accordingly be misaligned with the low regions of the front face, which may exacerbate the dishing in the low region.
Still another problem of this technique is that the cover layer must be deposited to a precise thickness so that the mask segments over the low regions are positioned at the desired end point. In some designs, for example, it may be desirable to deposit a relatively thin cover layer to reduce material costs and processing time. Such thin cover layers, however, may not be thick enough to position the mask segments at a desired endpoint. Thus, lithographically patterning resist over the low density fields also restricts the design flexibility of integrated circuits and semiconductor manufacturing processes.
In light of the need to form a planar surface over low density fields, and the problems associated with lithographic processing techniques, it would be desirable to develop a method for forming a globally planar surface over low density fields on a wafer that reduces costs, improves accuracy, and provides design and processing flexibility.
The present invention is a method for forming a planar surface over low density fields on a semiconductor wafer that has a contoured front face with a low region between high points. In accordance with one embodiment of the method, a fill layer is deposited over the front face to conform to the contour of the front face and form a depression in the fill layer positioned above the low region. A cover layer is then deposited over the fill layer to fill at least a portion of the depression. The cover and fill layers are selectively removable from the wafer using suitable etching and planarization processes. A portion of the cover layer is then selectively removed from the fill layer to an intermediate endpoint at which the upper portions of the fill layer are exposed, and the only remaining portion of the cover layer is positioned in the depression of the fill layer The upper exposed portions of the fill layer are then removed from the wafer to form a shoulder on the fill layer over the high points of the wafer and a raised support feature extending upwardly from the shoulder over the low region. After the raised support feature is formed, the wafer is planarized to a final endpoint. The raised support feature supports the polishing substrate over the low region to substantially prevent dishing over the low region, and thus the method of the invention forms a uniformly planar surface over the low density field on the wafer without lithographic processing techniques.